1. Technical Field
The present invention relates to a semiconductor integrated circuit, and more particularly, to a circuit and method for generating a data output control signal.
2. Related Art
In general, as shown in FIG. 1, semiconductor integrated circuits include output drivers 11 and 12, a delay locked loop (DLL) 20, a command generator 30, and a data output control signal generating circuit 40.
Each of the output drivers 11 and 12 outputs data signals DQ and DQS in response to one of the delay locked loo clocks fclk_dll and rclk_dll corresponding to a data output control signal outen.
The delay locked loop 20 corrects the phase of an internal clock iclk such that the phase of an external clock CLK is synchronized with the phases of the data signals DQ and DQS to generate the delay locked loop clocks fclk_dll and rclk_dll.
The command generator 30 receives the external clock CLK and an external read command COMMAND synchronized with the external clock CLK and outputs an internal clock iclk and an internal read command rd_cmd of a burst length (BL).
The data output control signal generating circuit 40 receives the internal clock iclk and column address strobe (CAS) latency CL and outputs a data output control signal outen suitable for the column address strobe latency CL.
The CAS latency CL is information for determining the output position of data in the external clock CLK from the external read command READ.
A delay time tCMD exists until the internal read command rd_cmd reaches the data output control signal generating circuit 40. In addition, a delay time tDO exists until the delay locked loop clocks fclk_dll and rclk_dll output from the delay locked loop 20 reach the output drivers 11 and 12.
The delay locked loop 20 causes a phase difference −tDO between the delay locked loop clocks fclk_dll and rclk_dll and falling and rising edges of the external clock CLK in order to compensate for the delay time tDO.
Therefore, the data output control signal generating circuit 40 compensates for the delay locked loop clock fclk_dll to have a delay time tDO+tCMD, latches the internal read command rd_cmd, and compensates for the delay time tDO+tCMD through an internal circuit structure, thereby synchronizing the phase of the data output control signal outen with the phase of the external clock CLK. The reason why the delay locked loop clock fclk_dll is used to latch the internal read command rd_cmd is to obtain a timing margin of ½tCK.
As such, the data output control signal generating circuit uses a data pre-fetch method. When the time required to convert parallel data into serial data is 2tCK, the data output control signal outen should be generated at a time (CL−2)*tCK. Therefore, as shown in FIG. 2, a general data output control signal generating circuit may include CL−1 flip-flops FF, CL−2 delay chains DC, and a plurality of AND gates AND for performing an AND operation of each CAS latency CL and the delay locked loop clock fclk_dll for each CAS latency CL. In addition, the data output control signal generating circuit includes a multiplexer MUX for selecting a signal corresponding to the CAS latency CL among data output control signals OE<3:8> output from circuits provided for each CAS latency CL and outputting the selected signal. For example, a circuit corresponding to CL6 includes an AND gate AND for performing an AND operation of CL6 and the delay locked loop clock fclk_dll, four delay chains DC6 for sequentially delaying an output signal of the AND gate AND, and five flip-flops FF for sequentially outputting the internal read command rd_cmd according to the output signal of the AND gate AND or output signals of the four delay chains DC6.
The sum of delay time of the delay chains for each CAS latency CL should be tDO+tCMD. Therefore, a delay time of one delay chain for each CAS latency CL is (tDO+tCMD)/CL−2.
Next, the operation of the data output control signal generating circuit according to the related art when CL is 6 will be described with reference to FIG. 3.
First, the AND gate AND outputs a fourth delay clock fdll_clkp<4>, and the four delay chains delay the signal by (tDO+tCMD)/4 to output zeroth to third delay clocks fdll_clkp<0:3>.
The zeroth to fourth delay clocks fdll_clkp<0:4> each have a delay of −tND, that is, (tDO+tCMD)/4.
The five flip-flops FF latch the internal read command rd_cmd and output the latched signal according to the zeroth to fourth delay clocks fdll_clkp<0:4>.
A fourth output enable signal oe<4> is output from the flip-flop FF, and the fourth output enable signal oe<4> is output as the data output control signal outen from the multiplexer MUX since CL is 6.
A phase difference tDO+tCMD occurs between the zeroth delay clock fclk_clkp<0> and the delay locked loop clock fclk_dll. Therefore, the data output control signal generating circuit according to the related art inversely compensates for a zeroth internal synchronization signal ioe<0> generated from the zeroth delay clock fclk_clkp<0> according to the first to third delay clocks fdll_clkp<1:3> to remove the phase difference tDO+tCMD, thereby outputting the fourth output enable signal oe<4>.
However, the data output control signal generating circuit of the semiconductor integrated circuit according to the related art has the following problems.
First, the delay clock fdll_clkp output from each delay chain needs to have a setup time tS and a hold time tH in order to latch each internal synchronization signal ioe. Since each delay clock fdll_clkp has a delay −tND, tCK>tNS+tS+tH should be satisfied. Therefore, when tCK is reduced, it is difficult to satisfy the above-mentioned relationship. As a result, there is a limitation on an available frequency.
Second, it is necessary to exactly divide the delay time of each delay chain into (tDO+tCMD)/CL−2. However, a modeled delay chain does not adapt to PVT (process, voltage, and temperature) variation, which makes it difficult to exactly divide the delay time. As a result, errors may occur in the phase of the data output control signal.
Last, CL−2 delay chains and CL−1 flip-flops are needed for each CAS latency CL. Therefore, as the CAS latency CL increases, the number of delay chains and the number of flip-flops become larger, which results in an increase in the layout area.